1. Field
This disclosure relates generally to electronic circuits, and more specifically, to a phase-locked loop (PLL) having a feedback clock detector circuit and method therefor.
2. Related Art
A PLL is used to generate a clock signal from a reference clock and typically includes a phase-frequency detector (PFD), a charge pump, and a voltage controlled oscillator (VCO). A feedback signal is provided from the output of the VCO to the PFD to adjust a frequency of the VCO. The generated clock signal may be at the same frequency as the reference clock signal or at some fraction or multiple frequency.
In some systems, the feedback circuit cannot operate as fast as the VCO output clock. The VCO output clock frequency is the frequency of the VCO or some multiple thereof. When a reference signal is present, but the feedback signal is not, the PFD enables the injection of current in a loop filter of the PLL to increase the frequency of the VCO. If the VCO output clock frequency increases to a point beyond which the feedback circuit can control, an unstable condition may develop, causing the VCO to “runaway”, or speed up to the maximum frequency of the VCO. The PLL may remain unlocked and be in an unrecoverable condition because of the inability of the feedback circuit to correct the VCO output clock frequency. A system being clocked by the PLL may then be non-functional.
Therefore, what is needed is a PLL that solves the above problems.